Implementation of Shift Registers ( shift to left )

Registers are just n-bit, where n>1, structures consisting of Flip Flops. A common clock is used for each FF in the register. In this entry, the implementation of shift register is presented. The design consists of 16 bit shift to left register as shown in Figure 1.

Figure1: Shift Register to Left

Input signal en used to enable the shift operation. The data from outside shift register will be feed into the module by lsb signal. Figure 2 show the Verilog code for this Shift Register for 16-bit.  As you can notice, the used of a concantenation operator is symbolized by { }.

Figure 2: Shift_Register of Verilog Code

Figure 3 shows the simulation waveform for shift register to the left. If you notice on the output Q, the pattern seems like 2à4à8à16à32à… (decimal value) or 2à4à8à10à20à…(Hexadecimal value) for every positive edge clock triggered.  What I want to say here, this bit operation movement from right to left is equal to the data was multiple by 2 for every clock cycle.

Figure 3: The output waveform for Shift Register to left

The implementation is on DE1 board, where switch SW0 used as reset signal and switch SW1 used as en signal. The lsb signal is port at KEY1. All the outputs Q (16 bits) are assign to LEDR (7..0) and LEDG(7..0). At the same time, these output also assign to 7 segment, HEX3, HEX2, HEX1 and HEX0. in order to human eye can observe the bit movement by naked eye, I need to add clock divider to make frequency become longer compare with clock on the board. The overall block diagram to implement this design is shown in Figure 4.

Figure 4: Implementation of Shift Register to left on DE1 board.

Now enjoy to watch this following video how I demonstrate implementation of shift to left on DE1 board.