Finite State Machine (FSM)

Finite State Machine (FSMs) are widely used in digital systems, with their typical utilisation as the core of a datapath controller unit. Via algorithmic state machine (ASM) flowchart, an FSM is readily modelled in HDL.

In this post or probably on entire my blog, I would like to focus only on synthesizable models.

Basically there are two types of models of FSM. Moore and Mealy

In a Mealy machine, the next state (NS) and the outputs depend on both the present state (PS) and the inputs. Meanwhile, the NS of the Moore machine depends on the PS and the inputs, but the outputs depend on only the PS.

In this entry, I focus on how to design FSM based on Moore machine. Given Figure 1 below show a Moore machine, where the output Z depends only on the PS. From the flowchart, it is clear that, the FSM has 4 states, implying the minimum number of state variables is 2. Therefore two Flip Flops are required in state register.

Figure 1: ASM Flowchart of FSM

The functional block diagram of this FSM is shown in Figure 2. All FSMs have the general feedback structure. A state register (or memory) holds the values of the PS, and the value of the NS is formed from the inputs and the contents of the state register, which in this case, is consisted of edge-triggered flip-flops. 

Figure 2: Functional Block Diagram of FSM

The Verilog program describing FSM is given in code as shown in Figure 3. Coding style here has three separate coding blocks, one for the NS logic (a process block) , one for the state register (a process block), and one for the output logic ( an assign block).

Figure 3: The Verilog program for FSM

 In the QuartusII ALTERA sotware, you can depict the State Machine as shown in Figure 4 by go to ToolsàNetlist Viewersà State Machine Viewer. 

Figure 4: A State Machine Viewer Tools

It look so simple with three main function block stated in that Verilog Code. Ok have a nice day!