Structural Modelling vs Behavioral Modelling

Hi, I was asking by my student to know if there is different between structural modelling and behavioural modelling in term of logic resources and speed.

So in order to verify that question, we did some simple experiment. I want they construct a 16 bit up counter with using structural modelling and another using behavioural modelling.

In Structural modelling, we need start to construct T_Flip Flop, then followed by Four Bit Up Counter, Eight Bit Up Counter and finally Sixteen Bit Up Counter.

Basically the Sixteen Bit Up Counter consist of 2 Eight Bit Up Counter, and Eight Bit Up Counter consist of 2 Four Bit Up Counter. Meanwhile the Four Bit Up Counter is consist of 4 T Flip Flop as shown in Figure 1, Figure 2 and Figure 3.

Figure 1: Four Bit Up Counter

 Figure 2: Eight Bit Up Counter

Figure 3: Sixteen Bit Up Counter

To verify the functionality of the circuit, we need to program (download) it into the targeted device. The targeted device is Cyclone II EP2C20F484C7N using DE1 Development board. We need to add clock divider and four of seven segment components together with this Sixteen Bit Up Counter. We call it as the Top Level Design.

Figure 4: Top Level Design

To enable the counter to start count, we define switch SW0 as enable signal and push button KEY0 as a reset signal. We able to programmed it into the board.

Now we are modelling the Sixteen Bit Up Counter using Behavioural Modelling. This Verilog code you can easily get form template provided by QUARTUS II ALTERA.  Create a new blank Verilog file, then click EditàInsert Template.  In Verilog HDLàFull DesignsàArithmeticàBinary Counter. By default this design is 64 bit counter. So just change parameter WIDTH=16, to be a sixteen bit counter.

Figure 5: Template 

We did same method verification on the targeted device. This design also runs successful.

Then now the question, how we know design using structural modelling or behavioural modelling are better from the others in term of logic and speed. We can get this data from compilation report for overall design including clock divider and seven segment modules.

For structural modelling, the result shows 74 Logic elements was used and maximum frequency at 234.69 Mhz.

Figure 6: Compilation Report for Top Level Design using Structural Modelling for 16 bit Counter

Meanwhile for Behavioural Modelling the result shows 68 Logic elements was used and maximum frequency at 241.08 Mhz.

Figure 7: Compilation Report for Top Level Design using Behavioural Modelling for 16 bit Counter

As conclusion, the Behavioural modelling seems give advantage in term of resources and speed especially on this experiment by 8% reduction of Logic Element and 3 % of speed improvement.

You can verify again on my finding by reproduce again the comparison result and show to me your result.

Thanks again.