CLOCK DIVIDER

The behaviour of describing sequential logic must be synchronized to a single edge for example posedge edge or negedge edge of the single clock.   The common synthesized sequential logics are Shift Register, Counter and Finite State Machine.

In this post, I would like to grasp your attention on how the exactly clock appears in actual waveform captured using oscilloscope compare with output produced in waveform simulator. The targeted board is ALTERA DE1 board using ALTERA’s FPGA and QuartusII Software as my synthesis tool and waveform simulator.

This ALTERA DE1 board have 50Mhz clock crystal on board. This frequency will generate Period Time 20ns as shown in Figure1 in ideal form.

Figure 1: An ideal pulse of 50 MHz

Then I use RIGOL DS1102E digital oscilloscope to capture the actual waveform and the result as shown in Figure 2.

Figure 2: Actual 50 MHz on board oscillator.

As a conclusion, the output waveform on board clock oscillator is sine waveform which is different from our thoughts, pulse waveform.  

Now came back to main issue, here I will provide the implementation of clock divider using Verilog code. Figure 3 shows the Verilog code of clock divider. If you observe carefully this code, it’s based on a counter implementation. We just change the parameter value DELAY= number. 

  

Figure 3: A Clock Divider

Lets say we generate clock divider with DELAY=0, so that frequency become 25Mhz. Figure 4 shows simulation waveform and Figure 5 shows actual waveform capture from oscilloscope. Surprise right!

Figure 4: A 25 Mhz output waveform from simulator

Figure 5: A 25Mhz output waveform capture from oscilloscope.

Then after I increase the value of parameter DELAY, now you can start observe the output at oscilloscope become pulse waveform.

Figure 6 shows the frequency at 12.5 Mhz , (DELAY=1). 

Figure 6: A 12.5M Hz output waveform capture from oscilloscope.

Figure 7 shows the frequency at 6.250 M Hz when DELAY=2.

Figure 6: A 6.25 M Hz output waveform capture from oscilloscope.

Now you can generate some of the delay into your design by using this clock divider by changing the parameter DELAY. Have a nice day and see you in next tutorial.