Design a Sequential Multiplier

On the previous tutorial, I was presented how the Register Transfer Level (RTL) designs methodology is successful to design a GreatestCommon Divisor (GCD) core engine.

Here again the same method I would like to apply it into sequential multiplier unit.  In the book “Fundamentals of Digital Logic with VHDL Design” by Stephen Brown & Zvonko Vranesic, they also provide one example to design this sequential multiplier. However they name it as Shift-and-Add Multiplier.

Let’ me start with design specification.

We are going to design a multiplier to multiply two an 8-bit unsigned numbers to produces 16-bit product. For example 8-bit Data A multiply with 8-bit Data B and produce 16-bit Product.

Algorithmic modelling 

In this step, we can translate the design specification to produce the behavioural model of the multiplier. This model is expressed in terms of an algorithm as shown in Figure 1, and this should be completed with IO Block diagram of the top-level system as shown in Figure 2.

Figure 1: Algorithm in Psedo-Code for sequential Multiplier for 8-bit input (n=8)

Figure 2: Top-Level of Sequential Multiplier

RTL Modelling

The RTL Model is first provided in the form of an ASM flowchart as shown in Figure 3. Then from the ASM flowchart, we can construct the RTL control sequence table in the form of an RTL Code is derived as shown in Table 1.

Figure 3: the ASM Flowchart of Sequential Multiplier

Table 1: The RTL-CS Table

Datapath

Figure 4 shows the datapath circuit for the sequential multiplier. The datapath consist of two shift registers, namely shift-left register for data A and shift-right register for data B. Other components are adder, multiplexer and register to store the Product (result).

Figure 4: Datapath of Sequential Multiplier

Meanwhile Figure 5 shows the top level datapath using Verilog code.

Figure 5: A Verilog Datapath code

Control Unit

The Verilog program in figure 6 shows how the control unit is constructing using Moore Model. There are three separate blocks, Next-State Logic block, State Register block and Output Logic block.

Figure 6: Verilog Code for Control Unit Sequential Multiplier

Waveform Simulation

Figure 7 show example waveform simulation to perform multiplication of hexadecimal number of FFh multiply with FFh. The product should be FE01h. In decimal number represents 255 x 255 = 65025. Inputs A and B are define as FF hexadecimal respectively. The sequential multiplier will be start the processing the data according to control unit. You can verify the state movement by State_Y output. Signal output valid will be asserted in state S3 to indicate the process of multiplication is finish and the valid result (output R) should be taken at the same clock. The state resume again at state S0.  As you can see for the worst case (FFh xFFh) the result should be ready around 18 clock cycles compare if I want to multiply 3 x 2 which is take only 5 cycles as shown in Figure 8.

Figure 7: Output Waveform Simulation for test vector FFh x FFh

Figure 8: Output Waveform Simulation for test vector 3h x 2h

Can you estimate the total clock cycles required if I would like to multiply Data A =00h with Data B= FFh ? It’s there are redundant clock have been waste? Can you do some improvement on this design? Please provide your feedback here!

CLOCK DIVIDER

The behaviour of describing sequential logic must be synchronized to a single edge for example posedge edge or negedge edge of the single clock.   The common synthesized sequential logics are Shift Register, Counter and Finite State Machine.

In this post, I would like to grasp your attention on how the exactly clock appears in actual waveform captured using oscilloscope compare with output produced in waveform simulator. The targeted board is ALTERA DE1 board using ALTERA’s FPGA and QuartusII Software as my synthesis tool and waveform simulator.

This ALTERA DE1 board have 50Mhz clock crystal on board. This frequency will generate Period Time 20ns as shown in Figure1 in ideal form.

Figure 1: An ideal pulse of 50 MHz

Then I use RIGOL DS1102E digital oscilloscope to capture the actual waveform and the result as shown in Figure 2.

Figure 2: Actual 50 MHz on board oscillator.

As a conclusion, the output waveform on board clock oscillator is sine waveform which is different from our thoughts, pulse waveform.  

Now came back to main issue, here I will provide the implementation of clock divider using Verilog code. Figure 3 shows the Verilog code of clock divider. If you observe carefully this code, it’s based on a counter implementation. We just change the parameter value DELAY= number. 

  

Figure 3: A Clock Divider

Lets say we generate clock divider with DELAY=0, so that frequency become 25Mhz. Figure 4 shows simulation waveform and Figure 5 shows actual waveform capture from oscilloscope. Surprise right!

Figure 4: A 25 Mhz output waveform from simulator

Figure 5: A 25Mhz output waveform capture from oscilloscope.

Then after I increase the value of parameter DELAY, now you can start observe the output at oscilloscope become pulse waveform.

Figure 6 shows the frequency at 12.5 Mhz , (DELAY=1). 

Figure 6: A 12.5M Hz output waveform capture from oscilloscope.

Figure 7 shows the frequency at 6.250 M Hz when DELAY=2.

Figure 6: A 6.25 M Hz output waveform capture from oscilloscope.

Now you can generate some of the delay into your design by using this clock divider by changing the parameter DELAY. Have a nice day and see you in next tutorial.